Computer Architecture and Organization (CT 211) - Exam
THE UNIVERSITY OF DODOMA
COLLEGE OF INFORMATICS AND VIRTUAL EDUCATION
SCHOOL OF INFORMATICS
UNDERGRADUATE UNIVERSITY EXAMINATIONS
FIRST SEMESTER 2018/2019
CN 210: COMPUTER ARCHITECTURE AND ORGANIZATION
Date: 25th February, 2019
Time allocated: 3 Hours
Instructions:
- This examination consists of two sections.
- Answer ALL questions from Section A and ANY TWO questions from Section B.
- All University of Dodoma Examination Regulations Apply.
SECTION A (60 Marks)
Question One
a) Differentiate between computer organization and computer architecture? (2.5 Marks)
b) State at least three basic functions of the computer? (2.5 Marks)
c) With the help of diagram describe the structure of central processing unit (CPU). (2.5 Marks)
d) Explain the computer level hierarchy. (2.5 Marks)
Question Two
a) State the principle of Equivalence of hardware and software (2 Marks)
b) Who is known as the father of computing and why? (4 Marks)
c) How many:
i. Milliseconds (ms) are in 1 second?
ii. Microseconds (µs) are in 1 second?
iii. kilobytes (KB) are in 1 gigabyte (GB)?
iv. Bytes are in 20 megabytes? (4 Marks)
Question Three
a) What is overflow and how can it be detected? How does overflow in unsigned numbers differ from overflow in signed numbers? (3 Marks)
b) With example(s) explain different ways of representing signed numbers. (3 Marks)
c) Represent the following decimal numbers in binary using 8-bit signed magnitude, one’s complement, and two’s complement:
i. 77
ii. -42 (4 Marks)
Question Four
a) What is a biased exponent, and what efficiencies can it provide? (2 Marks)
b) Convert the following to the specified radix:
i. (10110.101)₂ to base 10
ii. (34.625)₁₀ to base 4 (4 Marks)
c) Show the IEEE 754-bit patterns for the following single precision numbers:
i. +2⁻¹²⁸
ii. -1.01011 × 2⁻¹²⁶ (4 Marks)
Question Five
a) What is an Instruction Set Architecture (ISA)? (2 Marks)
b) Explain the difference between register-to-register, register-to-memory, and memory-to-memory instructions. (4 Marks)
c) With example(s), explain the following addressing modes:
i. Direct addressing mode
ii. Indirect addressing mode
iii. Index addressing mode
iv. Immediate addressing mode (4 Marks)
Question Six
a) Given the following arithmetic statement
P = ((X-Y+Z) * (M * N-O))/(Q+R * S)
i. Transform the above arithmetic statement in the postfix notation. (1 Mark)
ii. Write an assembly program to evaluate the given arithmetic statement by using Two-address instructions and Zero-address instructions. (5 Marks)
b) Show how the following values would be stored by machines with 32-bit words, using little endian and then big endian format. Assume each value starts at address 10₁₆. Draw a diagram of memory for each, placing the appropriate values in the correct (and labeled) memory locations.
i. 456789A1₁₆
ii. 14148888₁₆ (4 Marks)
SECTION B (40 Marks)
Question Seven
a) If you are a computer buyer trying to get the best performance from a system, what features would you look for in its memory hierarchy? (5 Marks)
b) Explain briefly the three fields in a direct mapped cache address? How are they used to access a word located in cache? (5 Marks)
c) Suppose a computer using set associative cache has 2²¹ words of main memory and a cache of 64 blocks, where each cache block contains 4 words.
i. If this cache is 4-way set associative, what is the format of memory address as seen by the cache, that is, what are the sizes of tag set and word fields?
ii. To which set the memory address 1FAB68 map? (10 Marks)
Question Eight
a) What are the RISC design principles and how can they be achieved? (5 Marks)
b) Write the main characteristics of RISC Architecture. (5 Marks)
c) Why is a RISC processor easier to pipeline than a CISC processor? (5 Marks)
d) Describe how register windowing makes procedure calls more efficient. (5 Marks)
Question Nine
a) Briefly explain basic techniques to increase the instruction execution rate of a processor. (5 Marks)
b) With examples, explain the performance measures for the goodness of a pipeline. (9 Marks)
c) Describe the following:
i. Pipeline stall due to instruction dependency
ii. Pipeline stall due to data dependency (6 Marks)
END OF EXAMINATION PAPER